The size of integrated circuit (IC) packages continues to decrease even as the complexity and level of circuit integration in the IC packages continue to increase. This is particularly true in the case of system-on-a-chip (SoC) devices, in which most, if not all, of an electronic appliance is integrated onto a single integrated circuit (IC) die. Thus, relatively complex devices, such as cell phones, network interface cards (NICs), communication buses, and the like, are now being implemented as a single integrated circuit or perhaps only several integrated circuits.
In addition to packing as many circuits as possible onto a single integrated circuit (IC) die, manufacturers are also packing as many IC dies as possible onto circuit board. In order to further this objective, manufactures place IC dies as close together as possible on a substrate to thereby increase IC die density. However, in some designs, manufacturers also stack IC dies vertically in order to improve the packing density of the integrated circuit dies.
In a stacked chip arrangement, a first IC die is mounted on a substrate by means of, for example, a solder ball grid array (BGA). Next, a silicon (Si) interposer mounted on top of the first IC die by means of an attachment layer, such as an adhesive layer or die attach. A second IC die is then mounted on top of the silicon interposer by means of another attachment layer (i.e., another adhesive layer/die attach). Additional IC dies and silicon interposers may subsequently be added to the stack to further improve packing density. Such a stack of IC chips may be implemented on an open substrate or within a sealed IC package.
However, as IC dies are packed more closely and lead lines become ever smaller, some well-known problems associated with IC manufacturing become aggravated. The cracking of solder joints connecting IC dies to substrates may cause a circuit board assembly to become defective. Thus, it is desirable to maintain a high level of solder joint reliability (SJR).
But, solder joints frequently crack due to thermal stresses encountered during manufacturing or during operation. Alternate cycles of heating and cooling may cause the substrate to warp, particularly as a result of shrinkage that occurs as the substrate cools. The coefficient of thermal expansion (CTE) of a silicon die is significantly less than the CTE of a substrate. The solder joints of a ball grid array connecting an IC die to a substrate are very fine. As the substrate warps, some of the solder joints may crack, thereby causing defects. This substrate warping is particularly damaging to stacked assemblies of integrated circuit dies.
There exists a need in the art for integrated circuit (IC) devices that have improved solder joint reliability. In particular, there is a need in the art to reduce warping of stacked die integrated circuit (IC) packages caused by the warping of the substrate due to thermal changes in the substrate.